Regviz

Microchip Technology /ATSAME70Q20 /XDMAC /XDMAC_CHID[20] /CIS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CIS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAMV71J21/XDMAC/XDMAC_CHID[4]/CIS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BIS)BIS 0 (LIS)LIS 0 (DIS)DIS 0 (FIS)FIS 0 (RBEIS)RBEIS 0 (WBEIS)WBEIS 0 (ROIS)ROIS

Description

Channel Interrupt Status Register (chid = 0)

Fields

BIS

End of Block Interrupt Status Bit
LIS

End of Linked List Interrupt Status Bit
DIS

End of Disable Interrupt Status Bit
FIS

End of Flush Interrupt Status Bit
RBEIS

Read Bus Error Interrupt Status Bit
WBEIS

Write Bus Error Interrupt Status Bit
ROIS

Request Overflow Error Interrupt Status Bit

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data